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MAX2769
Universal GPS Receiver
Table 2. Output Data Format
INTEGER
SIGN/MAGNITUDE
UNSIGNED BINARY
TWO’S COMPLEMENT BINARY
VALUE
7
5
3
1
-1
-3
-5
-7
1b
0
0
0
0
1
1
1
1
1.5b
01
01
01
00
00
10
10
10
2b
01
01
00
00
10
10
11
11
2.5b
011
001
001
000
000
101
101
111
3b
011
010
001
000
100
101
110
111
1b
1
1
1
1
0
0
0
0
1.5b
10
10
10
11
11
01
01
01
2b
11
11
10
10
01
01
00
00
2.5b
101
100
100
011
011
001
001
000
3b
111
110
101
110
011
010
001
000
1b
0
0
0
0
1
1
1
1
1.5b
01
01
01
00
00
11
11
11
2b
01
01
00
00
11
11
10
10
2.5b
101
100
100
011
011
111
111
110
3b
011
010
001
000
111
110
101
100
Comparison Frequency = TCXO = = 20 MHz
? LO 1575 . 42 MHz
The PLL loop filter is the only external block of the syn-
thesizer. A typical PLL filter is a classic C-R-C network
at the charge-pump output. The charge-pump output
sink and source current is 0.5mA by default, and the
LO tuning gain is 57MHz/V. As an example, see the
Typical Application Circuit for the recommended loop-
filter component values for f COMP = 1.023MHz and loop
bandwidth = 50kHz.
The desired integer and fractional divider ratios can be
calculated by dividing the LO frequency (f LO ) by
f COMP . f COMP can be calculated by dividing the TCXO
frequency (f TCXO ) by the reference division ratio
(RDIV). For example, let the TCXO frequency be
20MHz, RDIV be 1, and the nominal LO frequency be
1575.42MHz. The following method can be used when
calculating divider ratios supporting various reference
and comparison frequencies:
? 20 MHz
RDIV 1
L O Frequency Divider = = = 78 . 771
? COMP 20M Hz
Integer Divider = 78(d) = 000 000 0100 1110
(binary)
Fractional Divider = 0.771 x 2 20 = 808452
(decimal) = 1100 0101 0110 0000 0100
In the fractional mode, the synthesizer should not be
operated with integer division ratios greater than 251.
Crystal Oscillator
The MAX2769 includes an on-chip crystal oscillator. A
parallel mode crystal is required when the crystal oscil-
lator is being used. It is recommended that an AC-cou-
pling capacitor be used in series with the crystal and
the XTAL pin to optimize the desired load capacitance
12
and to center the crystal-oscillator frequency. Take the
parasitic loss of interconnect traces on the PCB into
account when optimizing the load capacitance. For
example, the MAX2769 EV kit utilizes a 16.368MHz
crystal that is designed for a 12pF load capacitance. A
series capacitor of 23pF is used to center the crystal
oscillator frequency, see Figure 1. In addition, the 5-bit
serial-interface word, XTALCAP in the PLL Configuration
register, can be used to vary the crystal-oscillator
frequency electronically. The range of the electronic
adjustment depends on how much the chosen crystal
frequency can be pulled by the varying capacitor. The
frequency of the crystal oscillator used on the MAX2769
EV kit has a range of approximately 200Hz.
The MAX2769 provides a reference clock output. The
frequency of the clock can be adjusted to crystal-oscil-
lator frequency, a quarter of the oscillator frequency, a
half of the oscillator frequency, or twice the oscillator
frequency, by programming bits REFDIV in the PLL
Configuration register.
ADC
The MAX2769 features an on-chip ADC to digitize the
downconverted GPS signal. The maximum sampling
rate of the ADC is approximately 50Msps. The sampled
output is provided in a 2-bit format (1-bit magnitude
and 1-bit sign) by default and also can be configured
as a 1-bit, 1.5-bit, or 2-bit in both I and Q channels, or
1-bit, 1.5-bit, 2-bit, 2.5-bit, or 3-bit in the I channel only.
The ADC supports the digital outputs in three different
formats: the unsigned binary, the sign and magnitude,
or the two’s complement format by setting bits FORMAT
in Configuration register 2. MSB bits are output at I1 or
Q1 pins and LSB bits are output at I0 or Q0 pins, for I or
Q channel, respectively. In the case of 2.5-bit or 3-bit,
output data format is selected in the I channel only, the
Maxim Integrated
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